Referring to the drawings, FIG. 1 shows a conventional CMOS buffer circuit generally designated by the numeral 10. The two transistor circuit includes a P channel MOS pull-up transistor 12 having a source connected to a positive supply voltage Vcc and a drain connected to the buffer circuit output. Circuit 10 also includes an N channel MOS pull-down transistor 14 having a drain also connected to the output and a source connected to the system ground Vss. The gates of the two transistors 12 and 14 are connected in common to the circuit input.
The buffer circuit is designed to respond to a predetermined range of input voltages Vin and produce output voltage Vout which fall within a predetermined range. By way of example, in many applications a CMOS buffer must be capable of operating with input and output voltages which are compatible with TTL logic levels. In that case, the input voltage Vin must be at +0.8 volts or lower to provide a low logic level and +2.0 volts or more to provide a high logic level. In order to maximize the noise margin, the buffer 10 would normally be designed to have a trip point midway between these levels, namely 1.4 volts. The term trip point as used here means the point at the input voltage Vin is equal to the output voltage Vout.
The shortcomings of the conventional buffer 10 of FIG. 1 are best illustrated by briefly describing the operation of the buffer, with the input Vin starting at a logic low level and increasing to a logic high level. Transistors 12 and 14, like all MOS transistor, operate in one of three regions: (1) cut-off region, (2) linear region and (3) saturation region. The latter two regions are both commonly referred to as the active region, with the difference between the two depending primarily upon the magnitude of the drain-source voltage of the device.
Generally, an MOS device is in the saturation region and acts like a constant current source if the magnitude of the drain-source voltage is greater than or equal to the magnitude of the difference between the threshold voltage of the device and the gatesource voltage. Similarly, the device is generally in the linear region and acts like a resistance when the magnitude of the drain-source voltage is less than the magnitude of the difference between the threshold voltage and the gate-source voltage.
Assume initially that the input voltage Vin is at a low logic level, +0.8 volts for example, and the supply voltage Vcc is at a nominal +5 volts. Under these conditions, pull-down transistor 14 will be near the cut-off region (non-conductive) because the gate-source voltage of the device (+0.8 volts) is less than or very close to the threshold voltage of the device. Pull-up transistor 12 will be active since the gate-source voltage (+5 volts-+0.8 volts) is more than the threshold voltage of that device. Under these conditions, the output voltage Vout will be close to the supply voltage Vcc of +5 volts. Thus, the voltage drop across active transistor 12 will be small thereby indicating that the device is operating in the linear region.
As the input voltage increases and approaches the threshold voltage of pull-down transistor 14, transistor 14 will start to become conductive. The voltage across transistor 14 will still be large at this point so that the transistor will remain in the saturation mode (current source), as opposed to the linear mode (resistive). As transistor 14 starts to turn on, the output voltage Vout will begin to drop.
As the input voltage Vin increases further, and as the output voltage Vout decreases further, the voltage across the pull-up transistor 12 will increase causing the transistor to enter the saturation mode. Thus, both transistors 12 and 14 will be operating in the saturation mode, with each device demanding a particular current. Initially, the pull-down transistor 14 will dominate and require more current than can be supplied by the pull-up transistor 12. This will cause the output voltage to drop very rapidly, as is desired. As the voltage begins to equalize across the two transistor, both devices will be in a saturation mode and require essentially equal amounts of current. This is preferably at the trip point of the buffer where the input voltage Vin and output voltage Vout are equal and are at about +1.4 volts in the present example.
As the input voltage Vin increases, the voltage across the pull-down transistor 14 tends to drop causing the device to change from the saturation mode to the linear mode. The output voltage will thus continue to drop, although at a slower rate than when both devices were saturated. The pull-up transistor 12 will remain in the saturation mode due to the relatively large voltage across this device.
Once the input voltage approaches +2.0 volts, the gate-source voltage of pull-up transistor 12 will approach -3.0 volts. Assuming that the threshold voltage of transistor 12 is -1 volt, the drain-to-source voltage is equal to the difference between the gate-to-source voltage and the threshold voltage of the transistor. This will cause transistor 12 to enter the linear region. At this stage the output resistance of transistor 12 is lowered substantially and will cause the voltage across the pull-down transistor 14 to be even lower.
As the gate voltage of transistor 14 approaches +4 volts, the transistor will enter linear operation as well when the difference between the input and the threshold voltage surpasses the output voltage. Finally, at +4 volts, transistor 12 will enter the cut-off region and the output will go all the way to 0 volts.
As can be seen from the foregoing, the operation of the conventional buffer 10 depends largely on the interaction between the pull-up and pull-down transistors 12 and 14 and the threshold voltage of the two devices. Further, as will be explained, the trip point of the buffer is a function of many variables, including the absolute value of the supply voltage Vcc, noise on the supply voltage, noise on the ground line, process variations and temperature changes.
In many applications, the input to a buffer may originate on another chip so that the input signal Vin does not necessarily vary with variations of supply voltage Vcc. Assume for example that voltage Vin is at the minimum logic high level of +2.0 volts. If the supply voltage Vcc were to increase to +6 volts, the gate-source voltage applied to pull-up transistor 12 would be +4 volts. Although this may not be sufficient alone to cause the buffer to incorrectly change states, a small amount of noise in input Vin or on the circuit ground may be sufficient. Similarly, pull-down transistor 14 may have a nominal threshold voltage of +0.7 volts. However, this voltage may change significantly due to process variations and due to temperature changes.
In addition, there is a significant amount of inductance present in the bonding wires or leads which connect the power pads on the chip to the pins of the chip package. In many applications, there are relatively large current transients through these inductances which result in large voltage transients on the power connections inside the chip. These transients are typically not even uniform throughout the chip itself. Thus, for example, if the input Vin were at +0.8 volts, and a transient was present which caused the ground voltage Vss to momentarily drop to -1.0 volts, the threshold voltage of transistor 14 would be exceeded and the device would turn on thereby resulting in an erroneous change in buffer output state.
Variations in trip point of a buffer or erroneous changes in state can result in very significant timing errors. This is particularly true in view of the fact that the buffer is frequently used as the first gate on a chip which receives signals external to the chip. For example, in high speed devices, a class of circuits is used that is commonly referred to as Address Transition Detection (ATD) circuits. If the output of a buffer driving an ATD were to change state as a result of noise being present on the supply line, for example, the ATD would incorrectly initiate a sequence of events in the chip. These events would disrupt operation of the chip thereby resulting in the creation of more noise and incorrect results.
The present invention relates to a buffer circuit which overcomes the above-noted shortcomings of conventional buffer circuits. The trip point of the subject buffer circuit can be precisely set and is immune to large amounts of noise present on the power supply and ground lines. Further, the trip point is stable with respect to process variations and with respect to temperature variations.
These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.